Testability is a concept which can be described as an improvement in Very Large Scale Integrated circuit design which enhances the ability of the chip manufacturer, the original equipment manufacturer who installs the chips on a circuit board, and the end user, to determine the adequacy of a particular piece of integrated circuit to perform the task it was designed for. Testability can be seen as having several components, including performance characteristics such as speed and consistency of throughput, consistency of throughput in the face of changing environmental conditions, correct performance of particular logic gates and combinational logic structures, correctness of the physical design in terms of whether and how true it is to the logical design characteristics specified, etc. The enhancements and features described in this application work together as a system to provide improvements in testability and, at the same time, provide for more efficient use of available semiconductor area ("silicon real estate"). Testability at the chip level can support module, board, or system level testability.
Different varieties of test systems have been built into Large Scale Integrated (LSI) and Very Large Scale Integrated (VLSI) circuit chips to improve testability. One particular example includes the patent issued to Lyon, U.S. Pat. No. 4,660,198, built specifically for detecting data errors at the earliest point that an error occurs in a combinational logic processing stream. This finds the errant logic by capturing data output from any point in the processing stream based on the first error found.
A different scheme for building testability into chips is described in Van Brunt, U.S. Pat. No. 4,357,703. Van Brunt contemplates the use of a control register for controlling the transmission gates (10, 23, 13, and 32), the operand generator and accumulator (22), and the output generator and accumulator (34), in order to control the input to the main function under test (11) and direct its output for analysis. Test data is input through the control shift register and the test is controlled through the test control input. As chips become more complicated and larger, it becomes helpful to include things like specialized flip-flops for holding test operands as they progress through complicated internal logic segments deep within the chip. Such a system is described in U.S. patent application Ser. No. 046,218.
Scan testing of various kinds besides the ones described in this invention can be used with this invention, and they can easily be implemented without consuming additional I/0 pins. For a discussion on scan designs see "Testing Semi-Custom Logic" by McClusky, Semiconductor International, September 1985 pp. 118-123 and "Built in Self Test Techniques", McClusky, 1985 April IEEE Design & Test pp. 21-36.
Some of these and other design features and use considerations for testability are described in the articles "A Fast 20K Gate Array With On-Chip Test System" by Ron Lake in VLSI System Design, June 1986; "Checking Out VLSI With Standard Test Gear" by David R. Resnick, published in Electronics, May 26, 1986; and "Testability and Maintainability With a New 6K Gate Array" also by David Resnick in VLSI Design, March/April 1983. The information contained in these articles is incorporated herein by this reference.
As the number of gates in a VLSI chip goes up and as they become more and more application-specific in design, the need for simple, consistent testability characteristics becomes more and more important.
Along with testing for the correctness of logic, process characteristics which affect performance (such as variations in capacitance and resistance) can and should also be tested for.